High Performance Parallel Prefix Adders with Fast Carry Chain Logic

Binary adders are the basic and vital element in the circuit designs. Prefix adders are the most efficient binary adders for ASIC implementation. But these advantages are not suitable for FPGA implementation because of CLBs and routing constraints on FPGA. This paper presents different types of parallel prefix adders and compares them with the Simple Adder. The adders are designed using Verilog HDL code and simulated and synthesized using Xilinx ISE13.2 software tool and Cadence RTL compiler. Among all the adders, Kogge-Stone adder provides better performance in ASIC implementation but it is not suitable for FPGA implementation. In order to make it suitable for FPGA implementation, Kogge-Stone adder is modified using fast carry logic technique. The modified adder provides better performance over the Simple adder for the higher order bit widths. KeywordsFPGA, Binary addition, Carry tree adders, Prefix computation, Prefix addition.